1. Field of the Invention
The present invention relates to a designing apparatus, a designing method, and a designing program for a semiconductor integrated circuit.
2. Description of the Related Art
Many designing methods for semiconductor integrated circuits are known. For instance, Japanese Patent Application Laid-Open No. 2007-142282 and Japanese Patent No. 3800514 disclose technologies for placement of decoupling capacitance.
Japanese Patent Application Laid-Open No. 2007-142282 discloses a layout method for an integrated circuit in which a plurality of cells are placed. This layout method for an integrated circuit includes the steps of computing a value of decoupling capacitance, creating a virtual cell, placing the virtual cell, and placing the decoupling capacitance. The step of computing a value of the decoupling capacitance includes computing values of decoupling capacitance that are necessary for individual functional cells. The step of creating a virtual cell includes creating the virtual cell having a placement region that is necessary for placement of the decoupling capacitance of the computed value and the functional cell. When the virtual cell is placed, the decoupling capacitance is placed in the placement region of the virtual cell in the step of placing the decoupling capacitance.
In this method, capacitance characterized for each type of the cell is set in advance. In other words, the necessary decoupling capacitance is computed assuming that every circuit works in one clock period. Therefore, the decoupling capacitance cell becomes excessive so that a chip size or leakage power may increase.
Japanese Patent No. 3800514 discloses a method for adding decoupling capacitance in designing an integrated circuit. This method makes a computer execute the following ten steps:
1) the step of creating a plan view concerning the integrated circuit, the plan view including a macro having requirements of predetermined functional characteristics and the decoupling capacitance space;
2) the step of dividing the plan view into a plurality of regions;
3) the step of determining an intrinsic capacitance value for each region;
4) the step of determining a support decoupling capacitance value necessary for supporting power grid voltage of each region in the plan view;
5) the step of determining a necessary decoupling capacitance value for each region based on the support decoupling capacitance value and the intrinsic capacitance value;
6) the step of determining a decoupling capacitor area for each region with respect to the necessary decoupling capacitance value;
7) the step of deciding whether or not the integrated circuit is a type in which the decoupling capacitance should be added in a vacant region;
8) the step of reducing the area that can be used for a circuit in each region by an amount corresponding to the decoupling capacitor area necessary in the region if it is decided that the integrated circuit is not the type in which the decoupling capacitance should be added in a vacant region;9) the step of creating a rule of a reduced circuit layout for each region; and10) the step of correcting the plan view based on the rule.
This method estimates the decoupling capacitance necessary for each region when the layout is designed. Therefore, the decoupling capacitance cells of the entire chip may not fall within the chip size so that substantial backtracking of design may be caused, resulting in an increase of designing cost. In addition, if a sufficient space for the decoupling capacitance is secured in advance in an early stage of design, the backtracking of design is reduced, but the chip size may be increased excessively. As a result, manufacturing cost may increase.